Tuesday 9th August 2022

SOI Technology Lights Up the Next Wave of Photonics Solutions | Features | Feb 2021

[ad_1]

Silicon on insulator — today a standard in the electronics industry — is fast becoming the platform of choice for a photonics-based technological era.

CÉLINE CAILLER, ALAIN DELPY, AND CORRADO SCIANCALEPORE, SOITEC

Silicon has been the mainstay of micro-nanoelectronics since the late 1950s, being widely adopted for electronic devices and complementary metal oxide semiconductor (CMOS) technologies. In the early years of the semiconductor industry, germanium was the favored material for electronic applications due to its higher carrier mobility; however, innovations at Bell Labs in surface passivation by thermal oxidation processing enabled a breakthrough in silicon semiconductor technology in the second half of the 1950s. Thermally grown silicon dioxide layers significantly reduce the concentration of electronic states at the silicon surface to electrically stabilize such interfaces. This capability has helped fuel broad adoption of silicon as the main vector of Moore’s law in CMOS technology, driving its democratization to mass-market applications.
Courtesy of SOITEC.


Courtesy of SOITEC.


Notwithstanding its excellent properties for CMOS technologies, however, silicon was never meant to remain a purely electronic material.

In the early 2000s, an optical age
of silicon began to unfold1. The material’s broad transparency that spanned the short- and mid-wavelength infrared enabled silicon-based optics to blossom into a wide variety of photonics technologies that targeted applications in data communications, sensing, and advanced computing.

In optical communications, for example, the progressive adoption of power-efficient, high-speed, silicon photonic links has helped to address the growing demand for data transmission bandwidth and increase computing capabilities. The intrinsic capability of light to transmit signals with low latency and power dissipation, at ultrahigh data rates, can be scaled from backbone infrastructures to rack-level optical links, down to chip-to-chip photonic interconnects. However, silicon could not meet the necessary requirements of these integrated optics applications without the additional innovation of silicon-on-insulator (SOI) technology.

SOI photonics

The SOI material platform offers considerable advantages by leveraging the highly mature ecosystem of CMOS technology, as well as comparatively newer processing technologies that enable the transfer of very thin layers of material from one substrate to another. The so-called Smart Cut process, collaboratively developed by CEA-Leti and SOITEC, underlies the development of engineered wafers by stacking extremely thin (from 10 nm up to a few hundred nanometers) and perfectly uniform crystalline layers of semiconductors that could not be achieved using classic microelectronic technologies.

Based on this process, SOI technology can now replace traditional copper lines in data interconnects with submicrometer-wide silicon waveguides that send, receive, and process information using optical frequencies.

Furthermore, thanks to its inherent CMOS-compatibility, the SOI platform provides a cost-effective approach for optical chip design and high-volume manufacture that features scalable bandwidth, footprint, and functionality.

Beyond optical transceivers for the data center interconnect (DCI) market — which is today the technology’s most mature segment — SOI photonics is also enabling applications in novel computing architectures, Internet of Things (IoT) components, biosensors, and lidar systems. It will soon support advancements in quantum technologies.

By leveraging mature semiconductor manufacturing methods, engineered wafers that incorporate SOI technology offer a powerful approach toward broader adoption of integrated optics.

Basically, high-quality single-crystalline silicon layers ranging in thickness from a few nanometers to several microns can be transferred onto a buried oxide (BOX) layer that is wet-grown onto a silicon handle substrate. In photonics applications, the BOX layer ensures high optical isolation, passivation of surface states, and extremely low defect density, while the handle substrate provides mechanical stability. Notably, such manufacturing methods can scale SOI technology to 200- and 300-mm wafer formats to combine high-throughput manufacturing capability with standard CMOS processing, enabling the integration of digital and photonic functions (Figures 1 and 2).

Figure 1. A production line of 300-mm silicon-on-insulator (SOI) wafers at SOITEC in Bernin, France. Courtesy of SOITEC.


Figure 1. A production line of 300-mm silicon-on-insulator (SOI) wafers at SOITEC in Bernin, France. Courtesy of SOITEC.


Figure 2. A schematic view of a photonic SOI substrate (a). A tilted scanning electron microscopy view of a silicon waveguide fully etched into the top silicon layer (b). A cross-sectional SEM image of a twin-waveguide directional coupler etched into the top silicon layer (c). Courtesy of CEA-Leti.



Figure 2. A schematic view of a photonic SOI substrate (a). A tilted scanning electron microscopy view of a silicon waveguide fully etched into the top silicon layer (b). A cross-sectional SEM image of a twin-waveguide directional coupler etched into the top silicon layer (c). Courtesy of CEA-Leti.


Additionally, the Smart Cut process allows further integration of advanced materials on silicon and other substrates. These materials include germanium on insulator, group III-V compounds such as gallium arsenide and indium phosphide, and piezoelectric materials such as lithium tantalate or lithium niobate. All pave the way to optical systems that offer high-performance emission, modulation, or detection of light along with industrial scalability.
Figure 3. Within-wafer (a) and wafer-to-wafer (b) statistics of thickness nonuniformity in the top silicon layer on 300-mm photonic SOI wafers. A sampled population of over 2000 wafers is reported, while the data has been measured via 41-point wafer-scale ellipsometry (c). Specifically, within-wafer nonuniformity (a) reports the absolute range when considering all measured points among the whole wafer population, while wafer-to-wafer nonuniformity (b) refers to the 41-point average thickness deviation of each wafer with respect to the nominal target (red dashed line). Courtesy of SOITEC.


Figure 3. Within-wafer (a) and wafer-to-wafer (b) statistics of thickness nonuniformity in the top silicon layer on 300-mm photonic SOI wafers. A sampled population of over 2000 wafers is reported, while the data has been measured via 41-point wafer-scale ellipsometry (c). Specifically, within-wafer nonuniformity (a) reports the absolute range when considering all measured points among the whole wafer population, while wafer-to-wafer nonuniformity (b) refers to the 41-point average thickness deviation of each wafer with respect to the nominal target (red dashed line). Courtesy of SOITEC.


SOI technology is still evolving today to offer new capabilities for silicon photonics. For example, control over the thickness of silicon layers (Figure 3) has continuously improved to allow greater uniformity within a few nanometers and provide ideal optical behavior at both the device and circuitry levels. Similarly, silicon layer surface roughness (Figure 4) can be controlled at the atomic scale to minimize unwanted scattering and to stabilize waveguide index and the phase of optical signals. These properties are essential for low-loss and high-coherence applications, such as quantum silicon photonics or solid-state chip-based lidar.
Figure 4. Top-layer silicon surface roughness measured with 30- × 30-µm atomic force microscopy scans, showing SOI evolution over the last few years. Today, processing technology can deliver 300-mm photonic SOI wafers with angstrom-level hill-to-valley surface roughness, providing cutting-edge material quality to integrated optics applications. Courtesy of SOITEC.


Figure 4. Top-layer silicon surface roughness measured with 30- × 30-µm atomic force microscopy scans, showing SOI evolution over the last few years. Today, processing technology can deliver 300-mm photonic SOI wafers with angstrom-level hill-to-valley surface roughness, providing cutting-edge material quality to integrated optics applications. Courtesy of SOITEC.


Moreover, as Figure 3 shows, local nonuniformity should be managed at both within-wafer and wafer-to-wafer levels to increase fabrication yields and drive down production costs for silicon photonic chips. This is particularly important when scaling up for high-volume manufacturing.

The adoption of optics-based input/outputs will ultimately
provide server architectures with greater system
flexibility, scalable speeds, and cost-effective operations
that only CMOS-compatible SOI photonics can deliver.

With regard to manufacturability, the geometrical aspects associated with SOI wafers are also of critical importance. Managing the warp and bow of SOI substrates is essential in foundry equipment, including etching and lithography tool sets used for defining submicrometric silicon features.

Maintaining all of these SOI specifications is instrumental to controlling process window stability and optimizing fabrication yields for silicon photonics.

Reaching the core

With the advent of 5G networks, the steady growth of data traffic in today’s telecommunications infrastructures is driving increases in both transmission rates and computing capabilities2. Such a burst in data is challenging the ability of short-reach copper-based interconnects in data centers and server architectures to offer enough bandwidth at reasonable power dissipation. Optics-based telecommunications has the potential to solve this challenge, if photonic function­alities can be integrated on electronic chips and cards to help trigger the onset of a photonics-based computational era….

[ad_2]

Read More:SOI Technology Lights Up the Next Wave of Photonics Solutions | Features | Feb 2021